Rtl Design Jobs
Browse 21 exciting jobs hiring in Rtl Design now. Check out companies hiring such as OpenAI, Tenstorrent, WHOOP in Arlington, Fremont, Mesa.
Lead hands-on silicon implementation and optimization across circuits, RTL, memory, and physical design to deliver next-generation AI chips and tooling for OpenAI.
Lead technical customer success for Tenstorrent’s AI silicon by translating customer needs into RTL and platform requirements and coordinating delivery across hardware and software teams.
WHOOP seeks a Full Stack Software Engineer II to help build scalable design system components and translation infrastructure that power globally consistent web and mobile experiences.
Intel is hiring a CPU Physical Design Engineer to lead RTL-to-GDS implementation and signoff for E-Core/Atom microprocessors, optimizing power, frequency, and area.
Senior Design Engineer role at Micron to lead functional verification efforts for non-volatile memory designs using SystemVerilog, UVM, assertions and automation.
WHOOP seeks an iOS Engineer II in Boston to develop shared frameworks, design-system components, and internationalization capabilities for its global client platform.
Lead the design and RTL implementation of GPU power-management blocks at Samsung Austin, translating microarchitecture into robust, production-ready hardware and partnering closely with SoC and firmware teams.
Lead go-to-market for a deep-tech AI-for-chip startup by building the commercial team, closing high-ticket silicon and IP engagements, and leveraging an existing semiconductor network.
Analog Devices is hiring a Staff AI/ML Digital Design Engineer to lead complex RTL design work while embedding AI/ML-driven automation into digital design flows.
Analog Devices is hiring a Digital Design Engineer to architect and verify low-power, high-speed SerDes digital IP and mixed-signal block designs for advanced semiconductor products.
Intel is hiring a seasoned CPU RTL Design Engineer to drive RTL development, optimization, and microarchitectural specification for cutting-edge processor IP.
Lead verification for next-generation space-qualified ASICs and FPGAs on SpaceX's Starshield program, developing SystemVerilog/UVM testbenches, driving coverage closure, and supporting pre/post-silicon bring-up.
Lead RTL‑to‑GDSII implementation and advance physical design methodology for high‑performance processor and networking ASICs at Marvell's Westborough physical design team.
Intel Foundry is hiring a Physical Design Methodology and Automation Engineer to drive TFM development, regression automation, and physical design optimizations for high-performance SoC and IP implementations.
Lead end-to-end physical design for cutting-edge SoCs at a high-growth Series C space company building the most powerful satellites in orbit.
Intel is hiring a Design Engineer focused on neuromorphic computing to develop RTL, prototype on FPGA/emulation platforms, and collaborate across architecture, verification, and software teams to bring neuro-inspired silicon to product readiness.
Lead the design and delivery of high-performance, space-qualified ASICs and FPGAs for SpaceX's Starshield national security programs.
SpaceX Starshield is hiring a Sr. ASIC Design Verification Engineer to lead SystemVerilog-based verification and validation of next-generation space and ground ASICs/FPGAs for national security applications.
Lead the microarchitecture, RTL design, and front-to-back implementation of complex SoC subsystems at a VC-backed semiconductor startup advancing next-generation chiplet solutions.
Senior RTL Design Engineer needed to develop and optimize RTL for Intel's next-generation CPU microarchitecture, driving high-performance and power-efficient processor features.
Intel's ACE organization is hiring a Design Verification Engineer to create and execute UVM/SystemVerilog verification environments for next-generation CPU designs.
How much do rtl design jobs pay?
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