Sr. ASIC Design Verification Engineer (Starshield) - job 1 of 2
Skills
- SystemVerilog testbench and UVM experience
- Digital ASIC verification and testbench development
- Constrained-random verification and coverage-driven methodology
- Automation with Python and MATLAB
- RTL design familiarity and chip bring-up/post-silicon validation
- Strong problem-solving and object-oriented programming skills
Responsibilities
- Lead digital ASIC verification at block and system level and execute verification test plans end-to-end
- Develop SystemVerilog testbench infrastructure (UVM and non-UVM), including DSP block tests
- Implement and run regressions, manage code and functional coverage, and drive coverage closure
- Automate test-case generation using Python and MATLAB
- Contribute to pre-silicon verification, post-silicon validation, and chip bring-up
- Develop test harnesses, test sequences, and verification milestones
Education
- Bachelor's degree in electrical engineering, computer engineering, or computer science (required)
- Advanced degree in EE/CE preferred
Benefits
- Base salary with eligibility for long-term incentives (stock/options) and potential bonuses
- Comprehensive medical, vision, and dental coverage
- 401(k) retirement plan
- Short- and long-term disability insurance and life insurance
- Paid parental leave, paid vacation (approx. 3 weeks), and 10+ paid holidays
- Employee Stock Purchase Plan and other discounts and perks
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