Principal ASIC Design Engineer (Starshield)
Skills
- Expert RTL implementation (Verilog/SystemVerilog)
- ASIC and FPGA design experience
- Timing closure and constraint development
- Clock domain crossing and low-power design techniques
- Familiarity with bus protocols (AXI, AHB, etc.)
- Experience with embedded processors and multicore CPU subsystems
- Proficiency with EDA tools (VCS, Questa, IES, Spyglass) and FPGA tools (Vivado, Quartus)
- Scripting skills (Python, TCL)
Responsibilities
- Design digital ASICs and FPGAs, define micro-architecture and implement RTL in Verilog/SystemVerilog.
- Evaluate architectural trade-offs and derive specifications for subsystems and circuits.
- Partition functions between hardware and software with modem/DSP and RFIC teams.
- Provide timing constraints, support synthesis, timing closure, and formality checks with physical implementation team.
- Work with verification engineers to ensure full verification coverage and deliver synthesis/timing clean designs.
- Participate in silicon bring-up, lab validation, and development of automated test equipment.
- Support off-site testing and occasional travel as required.
Education
- Bachelor's degree in Electrical Engineering, Computer Engineering, or Computer Science (required)
Benefits
- Base salary plus potential long-term incentives (stock, options, cash awards)
- Potential discretionary bonuses and Employee Stock Purchase Plan
- Comprehensive medical, vision, and dental coverage
- 401(k) retirement plan
- Short and long-term disability and life insurance
- Paid parental leave, paid vacation (approx. 3 weeks), and paid holidays
- Paid sick leave in accordance with company policy
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