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Browse 23 exciting jobs hiring in Cadence now. Check out companies hiring such as Intel, Assured, InterImage in Reno, New Orleans, Houston.

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Posted 2 days ago
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Intel is hiring a CPU Physical Design Engineer to lead RTL-to-GDS implementation and signoff for E-Core/Atom microprocessors, optimizing power, frequency, and area.

Lead and scale a high-performing outbound BDR team at an AI-native health tech company focused on automating critical provider operations.

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InterImage Hybrid No location specified
Posted 5 days ago

Senior Hardware Design Engineer role focused on ASIC/FPGA/SoC design, verification, and physical implementation for a cleared government-contractor environment.

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Posted 6 days ago

Lead commercial operations for IFS Loops to build a repeatable GTM engine, drive adoption in the installed base, and scale revenue through disciplined execution and cross-functional governance.

Posted 11 days ago

Marvell is hiring a Staff Analog Layout Engineer in Santa Clara to lead layout and verification of high-speed and precision analog IP using Cadence Virtuoso across multiple process nodes.

Posted 13 days ago

Lead end-to-end physical design for cutting-edge SoCs at a high-growth Series C space company building the most powerful satellites in orbit.

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Atom Computing Hybrid Boulder, CO or Austin, TX
Posted 14 days ago

Lead the architecture, RTL, verification, and silicon bring-up of mixed-signal ASICs that power Atom Computing’s neutral-atom quantum computers while shaping the long-term silicon roadmap.

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Posted 16 days ago

Elevate Semiconductor is hiring a Senior Analog Design Engineer in San Diego to lead design and optimization of high-performance analog CMOS circuits for ATE products.

Solidigm Hybrid Rancho Cordova, CA, United States
Posted 16 days ago

Senior engineer to build and own SPICE simulation flows and Virtuoso-based CAD automation that accelerate analog/mixed-signal design productivity and improve simulation-to-silicon correlation.

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Posted 16 days ago
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Lead frame cellset integration and validation for Intel Foundry, ensuring accurate scribeline layouts and tapeout integrity across lithography and metrology processes.

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Posted 17 days ago
Inclusive & Diverse
Rise from Within
Mission Driven
Diversity of Opinions
Work/Life Harmony
Growth & Learning
Transparent & Candid
Customer-Centric
Snacks
Onsite Gym
Family Coverage (Insurance)
Medical Insurance
Dental Insurance
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Life insurance
Disability Insurance
Health Savings Account (HSA)
Flexible Spending Account (FSA)
Learning & Development
Paid Time-Off
401K Matching
Maternity Leave
Paternity Leave

Become a key contributor on Intel's DTP team building and automating density/fill solutions and PDK fill components to ensure manufacturability at advanced semiconductor nodes.

Posted 17 days ago

Cadence is hiring a Solutions Architect (AE) to lead PDK/technology file development and provide technical and business-facing support to semiconductor customers working on advanced process nodes.

Radiant is hiring a Senior Electrical Engineer to own multilayer PCB design and hardware architecture for robust reactor control systems at its El Segundo headquarters.

Entry-level Electrical Engineer (PCB Design) to support schematic capture, multilayer PCB layout, bring-up, and validation for reactor control systems at Radiant’s El Segundo HQ.

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Broadcom Hybrid USA-CA Irvine Alton Parkway Bldg 2
Posted 18 days ago

Senior-level analog/mixed-signal IC design role at a leading semiconductor company working on high-speed circuits, PLLs/clock generation, and data converters.

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Anduril Industries Hybrid Costa Mesa, California, United States; Santa Ana, California, United States
Posted 19 days ago

Senior Electrical Engineer (Manufacturing Test) to design PCBA-based test platforms, fixtures, and data-acquisition systems for high-quality production at Anduril's Costa Mesa/Santa Ana facilities.

Lead the microarchitecture, RTL design, and front-to-back implementation of complex SoC subsystems at a VC-backed semiconductor startup advancing next-generation chiplet solutions.

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Tenstorrent Hybrid Austin, Texas, United States; Santa Clara, California, United States; Toronto, Ontario, Canada
Posted 22 days ago

Tenstorrent is hiring a Signal Integrity Engineer to drive high-speed PCB and package design, simulation, and validation for next-generation AI processors across Santa Clara, Austin, or Toronto.

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Posted 23 days ago

Mythic seeks a Senior Silicon Emulation Engineer to develop and operate large-scale emulation platforms for AI accelerators and enable early software and performance validation before silicon.

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Astera Labs Hybrid San Jose, California, United States
Posted 23 days ago

Lead and grow the Package Design team to deliver HVM-ready IC packaging solutions (FCBGA/FCCSP, multi-die, chiplets) that enable Astera Labs' PCIe, CXL, and Ethernet connectivity products.

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A high-ownership technical lead role to design, simulate, layout, and drive first-silicon learning for highly integrated silicon photonic ICs at an early-stage photonics company.

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Posted 24 days ago

Tacit seeks a PhD-level Antenna Engineering Intern to design, simulate, and validate advanced wireless sensing antennas within a fast-moving hardware startup in San Francisco.

Posted 26 days ago

Marvell is hiring a Senior Staff Analog Layout SRAM Engineer in Burlington, VT to lead SRAM memory layout and sign-off verification efforts and drive automation and quality across custom memory designs.

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