Senior ASIC Physical Design Engineer
Skills
- Hands-on experience with Synopsys ICC2/Fusion Compiler, Cadence Innovus, or equivalent.
- Strong timing analysis, STA, and timing closure skills.
- Power optimization and physical verification experience (DRC/LVS, IR drop, EM).
- Familiarity with hierarchical and flat SoC design flows and ECO implementation.
- Scripting and automation proficiency (Tcl, Python) for flow development.
Responsibilities
- Execute end-to-end physical design flow for complex SoC blocks and top-level integration (synthesis, floorplanning, P&R, CTS, STA, physical verification).
- Perform timing closure and optimization across multiple corners and modes using industry-standard tools.
- Collaborate with front-end, RTL, verification, DFT, and packaging teams to ensure clean handoffs and predictable convergence.
- Work with external physical design service providers to review deliverables, resolve issues, and align schedules.
- Develop and maintain scripts and automation to improve flow efficiency and reproducibility.
- Support sign-off activities including DRC/LVS, IR drop, EM, and power analysis.
- Manage chip-level integration tasks, ECOs, and tapeout preparation.
- Contribute to methodology development, tool evaluation, and flow documentation, and support products through production and spaceflight.
Education
- Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field.
- Formal training or coursework in VLSI/ASIC physical design, timing analysis, and semiconductor technology.
Benefits
- Base salary range $170,000–$250,000 plus equity
- Comprehensive medical, dental, and vision coverage
- Paid time off and paid parental leave
- Life insurance and other standard benefits
- Remote-friendly work model and flexible policies
- Opportunities for professional development and technical growth
- Participation in cutting-edge space hardware projects and mission impact
Average salary estimate
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