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Intel is hiring a CPU Physical Design Engineer to lead RTL-to-GDS implementation and signoff for E-Core/Atom microprocessors, optimizing power, frequency, and area.

Marvell is hiring a Staff Analog Layout Engineer in Santa Clara to lead layout and verification of high-speed and precision analog IP using Cadence Virtuoso across multiple process nodes.

Lead full-chip and block-level physical implementation of advanced SoCs that power K2's high-power satellites, from synthesis through GDSII and sign-off.

Elevate Semiconductor is hiring a Senior Analog Design Engineer in San Diego to lead design and optimization of high-performance analog CMOS circuits for ATE products.

A high-ownership technical lead role to design, simulate, layout, and drive first-silicon learning for highly integrated silicon photonic ICs at an early-stage photonics company.

Experienced program manager needed to lead Wiring & Low Voltage Systems (LVS) design, integration, and supplier activities for Archer's all-electric eVTOL program in San Jose.

Marvell is hiring a Senior Staff Analog Layout SRAM Engineer in Burlington, VT to lead SRAM memory layout and sign-off verification efforts and drive automation and quality across custom memory designs.