Principal ASIC Design Verification Engineer (Starshield)
Skills
- SystemVerilog testbench and UVM/OVM/VMM methodologies
- Digital ASIC verification and coverage-driven verification
- Test plan creation and execution
- Python and MATLAB scripting for automation
- Constrained-random verification and coverage analysis
- RTL design familiarity and chip bring-up/post-silicon validation
- Strong object-oriented programming and coding skills
Responsibilities
- Lead digital ASIC verification at block and system level
- Develop and execute verification test plans, harnesses, and test sequences
- Build SystemVerilog testbench infrastructure (UVM and non-UVM) including DSP block testing
- Run regressions and drive code and functional coverage closure
- Automate test case generation using Python and MATLAB
- Contribute to pre-silicon verification, chip bring-up, and post-silicon validation
- Act as a hands-on self-starter to fully verify complex digital designs
Education
- Bachelor's degree in Electrical Engineering, Computer Engineering, or Computer Science required
- Advanced degree in EE or CE preferred
Benefits
- Base salary plus potential long-term incentives (stock, options, cash awards)
- Discretionary bonuses and Employee Stock Purchase Plan (ESPP)
- Medical, vision, and dental coverage
- 401(k) retirement plan
- Short- and long-term disability insurance; life insurance
- Paid parental leave
- Approximately 3 weeks paid vacation and 10+ paid holidays per year
- Paid sick leave per company policy and other employee discounts/perks
Average salary estimate
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