Sr. ASIC Design Engineer (Starshield) - job 1 of 2
Skills
- 5+ years RTL implementation and/or FPGA/ASIC development experience
- Proficient in Verilog/SystemVerilog and RTL design flows
- Experience with timing closure, synthesis, and EDA tool flows
- Familiarity with clock domain crossing and low-power design techniques
- Experience with bus protocols (AXI/AHB) and embedded processors
- Scripting skills (Python, TCL) and use of HDL simulators and lint tools
Responsibilities
- Design digital ASICs and FPGAs including micro-architecture, RTL (Verilog/SystemVerilog), and top-level integration
- Evaluate architecture trade-offs and derive subsystem/circuit specifications with modem/DSP and RFIC teams
- Collaborate with verification to develop and execute comprehensive verification plans
- Provide timing constraints and support physical implementation (synthesis, timing closure, formality)
- Participate in silicon bring-up, validation, and development of automated test lab equipment
- Support off-site testing and travel as required to complete hardware validation
Education
- Bachelor’s degree in Electrical Engineering, Computer Engineering, or Computer Science (required)
- Advanced degrees (MS/PhD) in related fields preferred but not required
Benefits
- Base salary plus potential long-term incentives (stock, options, or cash awards)
- Possible discretionary bonuses and Employee Stock Purchase Plan
- Comprehensive medical, vision, and dental coverage
- 401(k) retirement plan, short/long-term disability, and life insurance
- Paid parental leave, paid vacation (approx. 3 weeks), and 10+ paid holidays
- Paid sick leave per company policy
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