Post-silicon Validation and Debug Engineer
Job Details:
Job Description:
The Role and Impact
As a SoC Debug Engineer, you will play a pivotal role in ensuring Intel's cutting-edge products perform seamlessly, innovating at the intersection of hardware, firmware, and software. Join our team to shape the future of technology by driving exceptional system-on-chip (SoC) debug solutions, improving industry workflows, and defining strategies that contribute to Intel's global leadership in innovation. This position offers an exciting opportunity to collaborate with cross-disciplinary teams, influence technical direction across Intel, and develop solutions fundamental to delivering high-quality products to market.
Key Responsibilities
Perform low-level and complex debug across multiple systems, subsystems, or SoC levels for Intel products.
Develop validation plans and execute tests for multiple domain- and system-level features/flows in the SoC.
Develop and implement techniques for faster SoC and platform-level debug while isolating failing system components.
Utilize design-for-debug (DFD) tools and scripts to continuously improve debug discipline.
Conduct root cause analysis, resolve triage failures and marginality issues, and track SoC debug progress.
Collaborate with design, system validation teams, and high-volume manufacturing factories to characterize new device features and functionalities.
Qualifications:
Minimum Qualifications
Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field.
0-1+ years of experience with a Bachelor's degree or 0 years with a Master's degree in SoC design and debug or equivalent experience.
Proficiency in SoC design, architecture, and debug techniques, including DFD tools and methodologies.
Strong understanding of firmware and software integration in hardware systems.
Ability to apply debug workflows using advanced test methodologies and failure isolation techniques.
Preferred Qualifications
Master's degree in Electrical Engineering, Computer Engineering, or related disciplines.
Exposure to collaborating across design and validation teams to achieve debug readiness.
Familiarity with Graphics and Power Management flows in an SoC design.
Drive to influence technical strategies and align organizational goals with technical vision.
Job Type:
College GradShift:
Shift 1 (United States of America)Primary Location:
US, Oregon, HillsboroAdditional Locations:
US, California, FolsomBusiness group:
Silicon and Platform Engineering Group (SPE): Deliver breakthrough silicon and platform solutions that deliver industry-leading products today while also defining the next generation of computing experiences.Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of Trust
N/ABenefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.
Annual Salary Range for jobs which could be performed in the US: $105,650.00-149,150.00 USD
The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.
Work Model for this Role
This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.*
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.Average salary estimate
If an employer mentions a salary or salary range on their job, we display it as an "Employer Estimate". If a job has no salary data, Rise displays an estimate if available.
Intel is hiring a Packaging Module Development Engineer to develop and qualify thermal material and mechanical design solutions for high-volume semiconductor packaging.
Drive process integration and technology transfer at Intel Foundry to turn development innovations into reliable, high-volume semiconductor manufacturing solutions.
Lead development and validation of engine cycle models (NPSS) to shape high-performance turbine engines for Mach Industries' scalable defense platforms.
Support San Francisco's transportation projects as a Junior Engineer performing field inspections, design support, calculations, and reporting for municipal infrastructure and traffic programs.
An engineering role at AbbVie responsible for independently designing, testing, and improving products and processes while coordinating resources and mentoring technicians within a regulated healthcare environment.
SeaWorld San Diego is hiring a Design & Engineering Summer Intern to assist with drafting, document control, project coordination, and procurement while gaining practical engineering and construction-related experience.
Crusoe is hiring a Senior Manager, Controls Deployment to lead engineering teams deploying high-density EPMS and BMS infrastructure across multi-region construction sites.
Experienced equipment engineer needed to manage and maintain RIE, CVD/PVD tools and gas systems in Harvard's high-volume CNS nanofabrication cleanroom while supporting research processes, safety, and user training.
Applied Research Associate Engineer to conduct field-based erosion, sediment and stormwater research, perform water-quality sampling and analysis, and support HEC-RAS modeling and engineering design at OSU's Wooster facility.
Launch your engineering career at Rolls‑Royce as an entry-level Control Systems Engineer working on power and propulsion control systems in Indianapolis.
City and County of San Francisco seeks an Assistant Engineer (Mechanical) to perform field and office engineering duties supporting municipal design, inspection, and project documentation.
Intel Foundry is hiring a Process Integration Engineer in Hillsboro to develop and integrate front-end semiconductor process flows, improve yield, and enable device performance at advanced nodes.
Lead the architecture and scaling of production business systems, factory infrastructure, and analytics to enable Reliable Robotics' transition from prototype to certifiable autonomous aircraft production.
Senior Director to lead and grow the Solutions Architecture/Engineering (SASE) team, delivering technical pre-sales support and architecting colocation, networking and hybrid cloud solutions for enterprise and hyperscale customers across North America.
Mainspring Energy seeks a Staff Controls & Automation Engineer to lead design and deployment of scalable control systems and automation for its manufacturing operations.
🔮
Hi, I'm Risa! Your AI Career Copilot
you, just ask me below!
