CPU Power Optimization Engineer
Job Details:
Job Description:
Do Something Wonderful!
Intel creates world-changing technology that improves the lives of every person on the planet. Join us as we continue to innovate in high‑performance, low‑power CPU design.
Who We Are
Our CPU design organization delivers cutting-edge microprocessors with industry‑leading performance per watt. We build CPUs for desktops, servers, laptops, and emerging product families, consistently pushing IPC and power efficiency forward.
Who You Are
In this role on the Silicon Engineering Group, you will focus on power analysis and low‑power optimization for Intel CPUs. You will partner closely with design and architecture teams to drive solutions that elevate power efficiency and advance our product leadership.
Your responsibilities will include, but not limited to:
- Drive power optimization efforts across architecture and RTL
- Identify opportunities to reduce dynamic and leakage power
- Propose and guide implementation of low‑power RTL changes
- Conduct feature‑ and workload‑based power analysis
- Close gaps between measured and targeted power on CPUs in development
- Develop and enhance power analysis and optimization methodologies
- Collaborate with architecture and RTL owners to deliver measurable results
- Provide recommendations for future CPU power architecture
Qualifications:
You must possess the minimum education requirements and minimum required qualifications to be initially considered for this position. Additional preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Minimum Qualifications and Experience:
The candidate must have a Bachelor's degree in electrical/computer engineering, computer science or related field with 4+ years of experience. Or a Master's degree in the same fields with 3+ years of experience or a PhD in in the same fields with 1+ years of experience.
Your experience described above must be in the following:
- Low-power CPU design
- Dynamic and leakage power estimation and reduction at architecture, RTL, block synthesis, or circuit level
- RTL design and RTL-level power optimization strategies
Preferred Qualifications
- Proficiency with industry‑standard power estimation tools
- Scripting/automation skills
- Good understanding of CPU architecture and SoC‑level power behavior
- Experience driving RTL-level power optimization in collaboration with design teams
- Familiarity with Intel CPU architectures (strong plus)
Job Type:
Experienced HireShift:
Shift 1 (United States of America)Primary Location:
US, Texas, AustinAdditional Locations:
US, Oregon, HillsboroBusiness group:
Silicon and Platform Engineering Group (SPE): Deliver breakthrough silicon and platform solutions that deliver industry-leading products today while also defining the next generation of computing experiences.Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of Trust
N/ABenefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.
Annual Salary Range for jobs which could be performed in the US: $141,910.00-200,340.00 USD
The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.
Work Model for this Role
This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.*
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.Average salary estimate
If an employer mentions a salary or salary range on their job, we display it as an "Employer Estimate". If a job has no salary data, Rise displays an estimate if available.
Intel is hiring a Packaging Module Development Engineer to develop and qualify thermal material and mechanical design solutions for high-volume semiconductor packaging.
Drive process integration and technology transfer at Intel Foundry to turn development innovations into reliable, high-volume semiconductor manufacturing solutions.
Lead and scale Zapier’s infrastructure and platform engineering organization, driving an AI-first platform strategy that boosts developer velocity, reliability, and product delivery.
Project Engineer needed to support large-engine electrical systems as a manufacturing liaison focused on build issue resolution, quality improvements, and traceability enhancements.
IAV Automotive Engineering is hiring a Junior Test Engineer to support emissions testing, vehicle prep, and data validation for powertrain and OBD calibration projects.
NODA is hiring a Tactical Communications & Networking Engineer to design, deploy, and troubleshoot tactical radio and mesh networking solutions that enable resilient multi-platform autonomy in contested environments.
An engineering role at AbbVie responsible for independently designing, testing, and improving products and processes while coordinating resources and mentoring technicians within a regulated healthcare environment.
Blue Origin is hiring a senior fluids systems engineer to lead the design, development, and testing of reaction control and heat exchanger subsystems for the New Glenn upper stage.
Lead development and validation of engine cycle models (NPSS) to shape high-performance turbine engines for Mach Industries' scalable defense platforms.
ACCIONA seeks a Construction Engineering Coordinator to coordinate temporary and permanent works engineering, manage RFIs/submittals, and support field constructability for the SR400 Express Lanes Project in Georgia.
Support San Francisco's transportation projects as a Junior Engineer performing field inspections, design support, calculations, and reporting for municipal infrastructure and traffic programs.
Launch your engineering career at Rolls‑Royce as an entry-level Control Systems Engineer working on power and propulsion control systems in Indianapolis.
Intel Foundry is hiring a Process Integration Engineer in Hillsboro to develop and integrate front-end semiconductor process flows, improve yield, and enable device performance at advanced nodes.
Senior Director to lead and grow the Solutions Architecture/Engineering (SASE) team, delivering technical pre-sales support and architecting colocation, networking and hybrid cloud solutions for enterprise and hyperscale customers across North America.
Lead the design and delivery of complex mixed-signal and RF PCB assemblies for next-generation quantum sensors at Vector Atomic, collaborating across hardware and science teams to drive high-performance instrument development.
🔮
Hi, I'm Risa! Your AI Career Copilot
you, just ask me below!
