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Senior Emulation/Verification Application Engineer

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Job Description

Join our elite Application Engineering team for verification to work closely with the best AEs, PEs and R&D in EDA at a company listed in Fortune magazine and Great Place to Work  as one of the 2025 World's Best Workplaces™ for the sixth time!
As an integral member of the North America Field Applications Engineering (AE) Team, you will work directly with industry leading semiconductor and system companies to deploy Cadence’s market leading Emulation and FPGA prototyping platforms, Palladium and Protium. In this customer facing role you will provide the front line technical support in the pre and post-sales process and will work with team members to come up with innovative solutions to address our customers’ most challenging problems in emulation and prototyping. 
As part of the team, you will develop customer specific emulation and prototyping requirements, including advanced acceleration component development, methodology support, and operation and maintenance of Cadence’s emulation and prototyping tools and services. You will support technical evaluations and benchmark development for Cadence’s market leading tools such as  Palladium acceleration and emulation platform and Protium prototyping platform. You will create and conduct technical presentations and product demonstrations for customers.

Key Responsibilities

  • Establish technical credibility and rapport with the customer 
  • Work closely with an experienced team to  become the go-to expert for  technical inquiries and support for emulation and prototyping
  • Become part of a team that provides  in-depth technical assistance in collaboration with R&D to help support advanced acceleration/emulation/prototyping flows to secure design wins
  • Champion the customer needs and work with R&D and marketing to develop competitive and creative technical solutions
  • Learn  the competitive landscape and continuously work on differentiating Cadence’s solutions
  • Write technical product literature such as application notes and technical articles

 

Requirements


FPGA prototyping knowledge including compilation, debug and performance optimization on FPGA prototyping platforms 
Experience with hardware accelerators and emulators  
Education or experience in Verilog
Systemverilog 
Knowledge of design fundamentals such as architecture, micro-architecture, HDLs and Synthesis and timing

Lab or internship experience leveraging hands on experience with lab bring up, debug, chipscope and instrument usage 

Minimum:
M.Sc. or B.Sc. degree in Computer Science, Engineering, or related field 
Good understanding and knowledge of Object Oriented Programming and experience in one such programming language such as C++, Java, Python or Systemverilog 
Knowledge of Linux/Unix platforms and scripting languages such as Perl, TCL, Python 
Strong verbal and written communication skills in English 
Self-motivated and strong teamwork skills 
Strong problem solving skills

The annual salary range for California is $84,000 to $156,000. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.

We’re doing work that matters. Help us solve what others can’t.

Average salary estimate

$120000 / YEARLY (est.)
min
max
$84000K
$156000K

If an employer mentions a salary or salary range on their job, we display it as an "Employer Estimate". If a job has no salary data, Rise displays an estimate if available.

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EMPLOYMENT TYPE
Full-time, onsite
DATE POSTED
April 4, 2026
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